GaAs FET DEVICE AND CIRCUIT SIMULATION IN SPICE.

A GaAs FET model suitable for SPICE circuit simulations was developed. Its dc equations are accurate to about 1% of the maximum drain current. A simple but accurate interpolation formula for drain current as a function of gate-to-source voltage combines the square-law behavior just above pinchoff and the square-root law for larger values of the drain current. The ac equations, with charge-storage elements, describe the variation of the gate-to-source and gate-to-drain capacitances as the drain-to-source voltage approaches zero and when this voltage becomes negative. Under normal operating conditions the gate-to-source capacitance is much larger than the gate-to-drain capacitance. At zero drain-to-source voltage both capacitances are about equal. For negative drain-to-source voltages the original source acts like a drain and vice versa. Consequently the normally large gate-to-source capacitance becomes small and acts like a gate-to-drain capacitance. In order to model these effects it is necessary to realize that, contrary to conventional SPICE usage, there are not separate gate-to-source and gate-to-drain voltages. The present treatment of these capacitances permits simulations in which th drain-to-source voltage reverses polarity, as occurs in pass-gate circuits.