62.5 ps LSB resolution multiphase clock Time to Digital Converter (TDC) implemented on FPGA

被引：3
|
作者：
Mattada M. [1 ]
Guhilot H. [2 ]
机构：
[1] Dept. of Electronics, Sanjay Ghodawat University, Kolhapur
[2] Research Resource Center, Visvesvaraya Technological University, Belagavi
来源：
Journal of King Saud University - Engineering Sciences | 2022年 / 34卷 / 06期
关键词：
FPGA; FPGA TDC; Multiphase clock; Picosecond resolution; PVT insensitive; TDC; Time to Digital Converter;
D O I：
10.1016/j.jksues.2021.01.007
中图分类号：
学科分类号：
摘要：
A 13-bit Time to Digital Converter is implemented using multiphase clock technique. Xilinx's Virtex 5 FPGA platform is used to realize the TDC architecture. One PLL within the FPGA works as a clock synthesizer to multiply the reference clock to 500 MHz. Then the combination of PLL and DLL topologies are used to generate 16 phases of the clock, separated by 11.25°. Further, 16 phases are generated by inverting the first 16 phases. A resolution of 62.5 ps has been recorded. Measured INL and DNL are within 1 LSB. The present work is suitable for many critical applications due to its PVT insensitive and robust properties. © 2021 The Authors
引用
收藏
页码：418 / 424
页数：6
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