A Review of High-Resolution Audio Sigma-Delta Modulator

被引：0
|
作者：
Sun A. [1 ]
Wen P. [1 ]
Shao H. [1 ]
Wang A. [1 ]
Lu Y. [2 ]
Zhang B. [2 ]
Zeng Y. [2 ]
Zhang Z. [1 ]
机构：
[1] School of Microelectronics, Hefei University of Technology, Hefei
[2] Tianjin JinHang Computing Technology Research Institute, Tianjin
来源：
Dianzi Yu Xinxi Xuebao/Journal of Electronics and Information Technology | 2024年 / 46卷 / 05期
基金：
中国国家自然科学基金;
关键词：
Audio; High-Resolution; Sigma-Delta (Σ-Δ) Modulator;
D O I：
10.11999/JEIT231208
中图分类号：
学科分类号：
摘要：
Sigma-Delta (Σ-Δ) Analog-to-Digital Converter (ADC) is based on oversampling and noise shaping techniques to achieve high-resolution, and is characterized by low passive component matching requirements and simple structure. In high-resolution audio applications, Σ-Δ ADC has gained widespread attention and applications since it can achieve high dynamic range with good power efficiency. Recently, there has been a growing research trend in designing low-power, high-resolution audio ADCs using advanced processes and technologies. However, with process technology going to lower nodes and the reduction of supply voltages, the circuit design becomes more challenging. This paper reviews the state-of-the-art of the discrete-time and continuous-time design of high-resolution audio Sigma-Delta modulators, provides theoretical background for the design of high-resolution audio Sigma-Delta modulators, and gives research prospects. © 2024 Science Press. All rights reserved.
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页码：1874 / 1887
页数：13
相关论文
共 106 条
  • [1] INOSE H, YASUDA Y, MURAKAMI J., A telemetering system by code modulation Δ-Σ modulation[J], IRE Transactions on Space Electronics and Telemetry, SET-8, 3, pp. 204-209, (1962)
  • [2] HAO Zhigang, YANG Haigang, ZHANG Chong, Et al., An improved digital decimation filter for Sigma-Delta ADC[J], Journal of Electronics & Information Technology, 32, 4, pp. 1012-1016, (2010)
  • [3] KUMAR R S A, KRISHNAPURA N., Multi-channel analog-to-digital conversion using a delta-sigma modulator without reset and a modulated-sinc-sum filter[J], IEEE Transactions on Circuits and Systems I: Regular Papers, 69, 1, pp. 186-195, (2022)
  • [4] SAEED M A, KUMAR M, UMAPATHI B, Et al., Optimization of slew mitigation capacitor in passive charge compensation-based delta-sigma modulator[J], IEEE Transactions on Circuits and Systems II: Express Briefs, 70, 6, pp. 1821-1825, (2023)
  • [5] PARK H, NAM K Y, SU D K, Et al., A 0.7-V 870-μW digital-audio CMOS sigma-delta modulator[J], IEEE Journal of Solid-State Circuits, 44, 4, pp. 1078-1088, (2009)
  • [6] WANG Yanchao, DEY S, HE Tao, Et al., A hybrid continuous-time incremental and SAR two-step ADC with 90.5-dB DR over 1-MHz BW[J], IEEE Solid-State Circuits Letters, 5, pp. 122-125, (2022)
  • [7] LIU Qilong, BREEMS L J, BAJORIA S, Et al., A 158-mW 360-MHz BW 68-dB DR continuous-time 1-1-1 filtering MASH ADC in 40-nm CMOS[J], IEEE Journal of Solid-State Circuits, 57, 12, pp. 3781-3793, (2022)
  • [8] DALLA LONGA M, CONZATTI F, HOFMANN T, Et al., An intrinsically linear 13-level capacitive DAC for delta sigma modulators[J], IEEE Transactions on Circuits and Systems II: Express Briefs, 70, 4, pp. 1291-1295, (2023)
  • [9] MENG Lingxin, CHEN Junsheng, ZHAO Menglian, Et al., An 18.2mW 101.1dB DR fully-dynamic ΔΣ ADC with partially-feedback noise-shaping quantizer and CLS-embedded two-stage FIAs[C], 2023-IEEE 49th European Solid State Circuits Conference, pp. 393-396, (2023)
  • [10] WANG Hetong, ZHENG Zhongxu, PUN K P., A 13-level SC DAC achieving high linearity with a simple DEM for wideband CT DSMs[J], IEEE Transactions on Circuits and Systems II: Express Briefs, 70, 8, pp. 2754-2758, (2023)
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