Evaluation of electrical characteristics and trap-state density in bottom-gate polycrystalline thin film transistors processed with high-pressure water vapor annealing

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作者：
Kunii, Masafumi [1 ]
机构：
[1] Mobile Display Business Group, Sony Corporation, Atsugi, Kanagawa 243-0014, Japan
来源：
Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers | 1600年 / 45卷 / 2 A期
关键词：
This paper discusses electrical characteristics and trap-state density in polycrystalline silicon (poly-Si) used in bottom-gate poly-Si thin film transistors (TFTs) processed with high-pressure water vapor annealing (HWA). The threshold voltage uniformity of the HWA-processed TFTs is improved by 42% for N-channel and 38% for P-channel TFTs in terms of standard deviation; and carrier mobility is enhanced by 10% or greater for both N- and P-channel TFTs than those TFTs processed conventionally. Subthreshold swing is also improved by HWA; showing that HWA postannealing is effective for improving the Si/SiO 2 interface of the bottom-gate TFTs. Two types of TFTs having different poly-Si crystallinities are examined to investigate carrier transport in poly-Si processed by HWA postannealing. The evaluation of trap-state density for the two types of poly-Si reveals that HWA postannealing is more efficient for N-channel than for P-channel TFTs. Furthermore; HWA postannealing is more effective for poly-Si with high crystallinity to improve TFT characteristics. The analysis of the trap-state distributions and the activation energy of TFT drain current indicate that HWA deactivates dangling bonds highly localized at poly-Si grain boundaries (GBs). Thus; HWA postannealing effects can be interpreted by a GB barrier potential model similar to that applied to conventional hydrogenation. © 2006 The Japan Society of Applied Physics;
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页码：660 / 665
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