A low power adaptive spatio-temporal bus coding for crosstalk avoidance

The power consumption, wiring overhead and crosstalk in deep sub-micron on-chip buses are the main facts restricting the bus throughput. An adaptive spatio-temporal bus coding scheme is proposed to reduce crosstalk induced delay and power consumption in the buses. Firstly, on-chip bus is partitioned into two sub-buses by spatio coding to reduce the Worst-Case-Crosstalk (WCC). Then, decisions are made respectively in the two sub-buses whether the original code and inverted code should incur WCC through an arbiter CCA (Crosstalk Class Arbiter). In the case of both original and inverted codes in any sub-bus incurring WCC, a shielding pattern is transmitted; otherwise the WCC-free and energy saving code is transmitted. The proposed scheme is evaluated using the SPEC benchmarks. The results show that the proposed scheme improves the throughput by 62.59% to 81.62% over the un-coded approach and reduces the power consumption by 14.63% to 54.67% compared to the other similar schemes while eliminating the WCC with only 7 wires overhead for a 32 bit bus. The scheme achieves a good enhancement in dynamic power, wiring overhead, and performance.