A new CMOS grounded positive capacitance-multiplier and an up-to-date bibliography on capacitance multipliers

The capacitance multiplier circuits using a variety of analog building blocks have currently been receiving prominent attention in the technical literature. This paper presents a classical but unexplored method of synthesising capacitance multiplier and a new grounded positive capacitance multiplier circuit derived by following this approach which employs thirty-two MOSFETs (all operating in saturation) and provides an electronically-controllable capacitance multiplication factor while employing a single grounded capacitor and without using any passive resistors, all of which are desirable features from IC implementation viewpoint. The circuit compares well with the other CMOS-compatible capacitance multipliers known in the earlier literature. The workability of the proposed circuit has been established through SPICE simulations based on 0.18 µm CMOS technology parameters. In the last, in view of the recent surge of interest on capacitance multipliers, an up-to-date bibliography on capacitance multiplier techniques and circuits, covering the period 1966-July 2024, has been provided for the benefit of the readers. © 2024 Elsevier GmbH