VLSI design of a high-speed RSA crypto-coprocessor with reconfigurable architecture

Through analyzing and comparing the normal RSA algorithm to the modified modular exponentiation and Montgomery multiplication algorithm in the arithmetic level, a nested pipelined RSA crypto-processor architecture is presented. This architecture has high-speed and reconfigurable feature. Based on the architecture, an RSA crypto-processor with various speed and key size can be designed, and it is especially valuable for high speed, long key size applications. It is also suitable for low speed, long key size, and high security level applications, or configured as an IP core embedded in SoC platform. As an example, a high-speed 1024-bit RSA crypto-processor is implemented using 0.18 μm CMOS technology. The simulation result indicates that the encryption rate of the crypto-processor is more than 5000 times per second at 150 MHz clock frequency. The performance of the crypto-processor proposed is the best reported in the literature in China.