Low-power and area-optimized VLSI implementation of AES coprocessor for Zigbee system

被引：9
|
作者：
LI, Zhen-rong [1 ]
ZHUANG, Yi-qi [1 ]
ZHANG, Chao [1 ]
JIN, Gang [1 ]
机构：
[1] Key Laboratory, the Ministry of Education for Wide Band-Gap Semiconductor Materials and Devices, Xidian University, Xi'an, 710071, China
来源：
Journal of China Universities of Posts and Telecommunications | 2009年 / 16卷 / 03期
关键词：
This work was supported by the National Natural Science Foundation of China (60676053);
D O I：
10.1016/S1005-8885(08)60232-0
中图分类号：
学科分类号：
摘要：
引用
收藏
页码：89 / 94
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