High-voltage p-channel level shifter using charge-controlled self-isolation structure

被引：0

作者：

Yamazaki, Tomoyuki ^{[1
,4
]}

Kumagai, Naoki ^{[2
]}

Nishiura, Akira ^{[3
]}

Fujihira, Tatsuhiko ^{[3
]}

Seki, Yasukazu ^{[2
]}

Matsumoto, Takashi ^{[4
]}

机构：

[1] Fuji Hitachi Power Semiconductor Co., Ltd., 4-18-1 Tsukama, Matsumoto, Nagano 390, Japan

[2] Fuji Electric Advanced Technology Co., Ltd., 4-18-1 Tsukama, Matsumoto, Nagano 390, Japan

[3] Fuji Electric Device Technology Co., Ltd., 4-18-1 Tsukama, Matsumoto, Nagano 390, Japan

[4] School of Engineering, University of Yamanashi, 4-3-11 Takeda, Kofu 400, Japan

来源：

Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers | 2006年 / 45卷 / 9 A期

关键词：

In this paper; we report an area-effective 600V p-channel level shifter using a self-isolation structure without the degradation of blocking capability for the first time. To prevent the degradation of high-voltage isolation performance; the charge in a double reduced surface electric field (RESURF) structure is controlled at the border region between a high-voltage p-channel metal oxide semiconductor field effect transistor (MOSFET) and a high-voltage isolation region. Because of a divided p-offset region in the drift region of the high-voltage p-channel MOSFET and the high-voltage isolation region; parasitic current to the ground (GND) terminal through the isolation region can be ignored. By using the new high-voltage p-channel level shifter; a 400V level shift operation is confirmed. © 2006 The Japan Society of Applied Physics;

D O I：

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中图分类号：

学科分类号：

摘要：

Journal article (JA)

引用

页码：6914 / 6916

共 34 条

[1] High-voltage p-channel level shifter using charge-controlled self-isolation structure
Yamazaki, Tomoyuki
Kumagai, Naoki
Nishiura, Akira
Fujihira, Tatsuhiko
Seki, Yasukazu
Matsumoto, Takashi
JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS, 2006, 45 (9A): : 6914 - 6916
[2] HIGH-VOLTAGE SWITCHING P-CHANNEL STRUCTURE FOR CMOS ARCHITECTURES
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[3] Bias temperature reliability of p-channel high-voltage devices
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Pergoot, A
DePauw, P
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[4] SOA improvement of p-channel high-voltage SOI devices
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[7] Experimental and Numerical Studies on dV/dt Robustness of 1200 v High-Voltage Integrated Circuits Using Self-Isolation Structure
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[8] Electrical Characteristics of a High-voltage P-channel LDMOSFET Utilizing SOI Technology
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[10] High-Performance p-Channel LDMOS Transistors and Wide-Range Voltage Platform Technology Using Novel p-Channel Structure
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