Design of an L1 band low noise single-chip GPS receiver in 0.18 μ m CMOS technology

被引：0

作者：

Chen Y.-M. ^{[1
]}

Li Z.-Q. ^{[1
]}

Wang Z.-G. ^{[1
]}

Jing Y.-K. ^{[1
]}

Zhang L. ^{[1
]}

机构：

[1] Institute of Radio Frequency, Electronic Integrated Circuits, Southeast University

来源：

Journal of China Universities of Posts and Telecommunications | 2010年 / 17卷 / 03期

基金：

中国国家自然科学基金;

关键词：

CMOS RF receiver; GPS; Low IF; Satellite communications; Wireless communications;

D O I：

10.1016/S1005-8885(09)60463-5

中图分类号：

学科分类号：

摘要：

This article presents an L1 band low noise integrated global positioning system (GPS) receiver chip using 0.18 μm CMOS technology. Dual-conversion with a low-IF architecture was used for this GPS receiver. The receiver is composed of low noise amplifier (LNA), down-conversion mixers, band pass filter, received signal strength indicator, variable gain amplifier, programmable gain amplifier, ADC, PLL frequency synthesizer and other key blocks. The receiver achieves a maximum gain of 105 dB and noise figure less than 6 dB. The variable gain amplifier (VGA) and programmable gain amplifier (PGA) provide gain control dynamic range over 50 dB. The receiver consumes less than 160 mW from a 1.8 V supply while occupying a 2.9 mm2 chip area including the ESD I/O pads. © 2010 The Journal of China Universities of Posts and Telecommunications.

引用

页码：60 / 65

页数：5

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