An Adaptive and Low-Complexity Maximum Likelihood Sequence Detector for High-Speed PAM4 Wireline Transceivers

被引：0
|
作者：
Xu C. [1 ]
Lai M. [1 ]
Lyu F. [1 ]
Wang Q. [1 ]
Qi X. [1 ]
Luo Z. [1 ]
Li S. [1 ]
Zhang G. [1 ]
机构：
[1] College of Computer, National University of Defense Technology, Changsha
来源：
Jisuanji Fuzhu Sheji Yu Tuxingxue Xuebao/Journal of Computer-Aided Design and Computer Graphics | 2024年 / 36卷 / 03期
关键词：
4 pulse amplitude modulation; field programmable gate array; maximum likelihood sequence detection; serializer/deserializer; Viterbi algorithm; zero-forcing algorithm;
D O I：
10.3724/SP.J.1089.2024.20161
中图分类号：
学科分类号：
摘要：
The high-speed serial transceiver is the key component for high-performance chips such as CPUs, NICs and switches. The decision feedback equalization (DFE) is the main equalization circuit of the high-speed serial transceiver. However, the high bit error rate (BER) of conventional DFE in high inter-symbol interference (ISI) channels limits the rate increase of serial transceiver. An adaptive reduced-state sequence detector (ARSSD) with low complexity is proposed in this paper. The detector adopts maximum likelihood sequence detection (MLSD) structure to reduce the detection BER, combines the Viterbi algorithm and the set-partitioning algorithm to reduce the complexity of operations and adopts zero-forcing (ZF) algorithm based ISI parameter acquisition to achieve the adaptive detector parameters. In this paper, the behavioral simulation, circuit implementation and system verification of ARSSD are completed. The experimental results based on the analog front-end chip (AFEC) and the field programmable gate array (FPGA) show that: 12~64Gbps PAM4 signals are faded by −8~−18dB@16GHz channel, the detection BER of 32×4 parallel ARSSDs is reduced by two orders of magnitude compared to the conventional DFE, which is consistent with the behavioral simulation results. © 2024 Institute of Computing Technology. All rights reserved.
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页码：452 / 463
页数：11
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