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- [2] Balancing of Peak Currents between Paralleled SiC MOSFETs by Source Impedances 2017 THIRTY SECOND ANNUAL IEEE APPLIED POWER ELECTRONICS CONFERENCE AND EXPOSITION (APEC), 2017, : 800 - 803
- [4] Balancing the Switching Losses of Paralleled SiC MOSFETs Using a Stepwise Gate Driver 2021 IEEE ENERGY CONVERSION CONGRESS AND EXPOSITION (ECCE), 2021, : 5400 - 5406
- [5] Individual Control of Paralleled SiC-MOSFETs with Nano-Second Level Switching Timing Synchronization 2024 36TH INTERNATIONAL SYMPOSIUM ON POWER SEMICONDUCTOR DEVICES AND IC S, ISPSD 2024, 2024, : 188 - 191
- [7] Switching Current Imbalance Mitigation for Paralleled SiC MOSFETs Using Common-mode Choke in Gate Loop 2020 IEEE ENERGY CONVERSION CONGRESS AND EXPOSITION (ECCE), 2020, : 705 - 710