Design of Timing Driven Circuit for Ultra Large Array CMOS Image Sensor

Resolution is one of the most important indicators of CMOS image sensors. The higher the resolution, the larger the pixel array is. The increase in the lateral size of the pixel array places higher requirements on the driving capability of the timing-driven circuit. The increase in the vertical size also causes the delay to affect the generation of selection signal. This paper studies the timing driven circuit of an ultra large array CMOS image sensor. The pixel array is simultaneously driven to improve the driving ability of the timing-driven circuit when the size of the pixel array is determined, and the influence of the parasitic effect on the control signal line is analyzed. Reversely inserting method of the shift register clock is proposed. The reliability of the circuit is improved without the additional layout consumption. In addition, the size of the sensor is large, so the timing-driven circuit is designed as a repeatable unit, and then spliced. Based on the 110 nm CMOS process, an ultra large array CMOS image sensor timing driven circuit is designed, and a 2 k×2 k sample chip design is performed. With the two-share 5T pixel structure, the timing-driven circuit can switch between Rolling mode, binning mode, and global mode, high gain mode can be turned on to obtain good performance in low-light conditions. The pixel size of the sample chip is 6 μm×6 μm, the size of the unilateral row driving circuit is 2256μm×12288μm, the size of the overall chip is 19300μm×19500μm, the frame rate is 2frams per second, and the row selection time of each row is 24.36 μs. The difference from left and right is less than 5 ns. © 2021, Editorial Board of Journal of Tianjin University(Science and Technology). All right reserved.