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- [1] SVR: A Shard-aware Vertex Reordering Method for Efficient GNN Execution and Memory Access 2022 19TH INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC), 2022, : 165 - 166
- [2] Efficient Execution of Memory Access Phases Using Dataflow Specialization 2015 ACM/IEEE 42ND ANNUAL INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE (ISCA), 2015, : 118 - 130
- [4] Efficient MIP volume rendering via fast SIMD interpolation and memory access reordering Multimedia Tools and Applications, 2023, 82 : 10515 - 10534
- [7] MEGA: A Memory-Efficient GNN Accelerator Exploiting Degree-Aware Mixed-Precision Quantization 2024 IEEE INTERNATIONAL SYMPOSIUM ON HIGH-PERFORMANCE COMPUTER ARCHITECTURE, HPCA 2024, 2024, : 124 - 138
- [8] MEGA: A Memory-Efficient GNN Accelerator Exploiting Degree-Aware Mixed-Precision Quantization Proc. Int. Symp. High Perform. Comput. Archit., 1600, (124-138): : 124 - 138
- [10] MEMORY ACCESS REDUCTION METHOD FOR EFFICIENT IMPLEMENTATION OF FAST COSINE TRANSFORM PRUNING ON DSP 2010 IEEE INTERNATIONAL CONFERENCE ON ACOUSTICS, SPEECH, AND SIGNAL PROCESSING, 2010, : 1490 - 1493