Implementation of adders using XOR gates in quantum-dot cellular automata with physical verification

This paper presents a promising approach to nanoscale computing, offering significant advantages through the QCA technology. It suggests a highly efficient, scalable, and reliable multilayered QCA half and full adder circuits, leveraging a three-input QCA XOR gate. The proposed full adder layout demonstrates significant improvements in various parameters, including area, latency, and energy dissipation. In particular, it offers 17% greater area efficiency and utilizes 14 fewer cells compared to the best work existing work. We thoroughly evaluated energy dissipation using the QCADesigner-E tool. We also examined the cost functions, with a QCA-specific cost of 22 units, which is similar to 37% better than earlier designs. The architecture is strategically designed with externally accessible input and output nodes to ensure seamless scalability. Physical reliability is ensured through kink energy calculations for the suitability of higher-order circuit designs. Practical applications of the proposed blocks include their use in arithmetic logic units (ALUs), digital signal processors, and other modern processing and computing systems. This work sets a new benchmark for future developments in QCA technology, offering a robust, efficient, and versatile solution for advanced nano-processing and computing systems.