A compiler generation method for HW/SW codesign based on configurable processors

被引：0
|
作者：
Kobayashi, Shinsuke [1 ]
Mita, Kentaro [1 ]
Takeuchi, Yoshinori [1 ]
Imai, Masaharu [1 ]
机构：
[1] Dept. of Informatics and Math. Sci., Grad. School of Engineering Science, Osaka University, Toyonaka-shi, 560-8531, Japan
来源：
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences | 2002年 / E85-A卷 / 12期
关键词：
Adders - Algorithms - Application specific integrated circuits - Computer aided software engineering - Computer hardware description languages - Computer simulation - Embedded systems - Integrated circuit layout - Microprocessor chips - Program compilers - Reduced instruction set computing - Storage allocation (computer);
D O I：
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摘要：
This paper proposes a compiler generation method for PEAS-III (Practical Environment for AS1P development), which is a configurable processor development environment for application domain specific embedded systems. Using the PEAS-III system, not only the HDL description of a target processor but also its target compiler can be generated. Therefore, execution cycles and dynamic power consumption can be rapidly evaluated. Two processors and their derivatives were designed using the PEAS-III system in the experiment. Experimental results show that the trade-offs among area, performance and power consumption of processors were analyzed in about twelve hours and the optimal processor was selected under the design constraints by using generated compilers and processors.
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页码：2586 / 2595
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