Design of an Integrated Circuit Test System for DC Parameters

被引:0
|
作者
Zhang W. [1 ]
Wang J. [1 ]
Tong W. [2 ]
机构
[1] School of Microelectronics, Tianjin University, Tianjin
[2] Yangtze Memory Technologies Co., Ltd., Shanghai
关键词
DC parameters test; Field-programmable gate array; Integrated circuit test; Precision measurement unit; System error calibration;
D O I
10.11784/tdxbz201908008
中图分类号
学科分类号
摘要
As the integrated circuit industry develops rapidly, the chip testing costs for advanced integrated circuit account for a large proportion of the overall cost of chip production. Thus, designing reliable DC parameter automatic test systems with high precision and low cost is necessary. Accordingly, numerous studies have been conducted on integrated circuit DC parameter testing, and a test system has been proposed based on the field-programmable gate array(FPGA)that has been widely used in the embedded system. The designed system consists of several parts and follows the modular design principle. A precision measurement circuit was designed with 16 independently program-mable voltage output channels and one measurement circuit, which can provide and measure voltage up to ±30V and current up to ±500mA. To reduce the test cost and broaden the application range of the system, the FPGA that was programed using Verilog HDL, was employed to control the system. Additionally, the calibration coefficient of each test loop, which was obtained by linear fitting, was introduced to perfect the system and improve the test accu-racy. Therefore, the error caused by the device and analog circuit was calibrated, so that the excitation value applied to the device under the test is closest to the ideal value. During the test process, precise resistors were used as loads to verify the system performance under different measurement modes. The test results show that the FPGA-based DC parameter test system has a higher test accuracy and wider test range. The relative errors of the calibrated test systems are estimated within ±0.03%, indicating that the system can perform a DC parameter test of 3D NAND flash memory chips. © 2020, Editorial Board of Journal of Tianjin University(Science and Technology). All right reserved.
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页码:1288 / 1294
页数:6
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