An analysis tool towards fault tolerance systems based on AADL error model

Fault-tolerant embedded systems can provide the correct service with the active faults. It is important to verify the ability of fault tolerance in system design phase especially for safety-critical systems. Besides, the verification of models can reduce the cost of the system development. The Architecture Analysis and Design Language (AADL) and its Error Model Annex (EMV2) provide the ability to model a fault tolerance system. The error event, error propagation and error state machine provided by the AADL Error Model Annex can model an embedded system. However, there is a problem that whether the model satisfies the requirement of fault tolerance or not. We design a component-based algorithm to verify the ability of fault tolerance. The error and warning messages will be produced by our algorithm. Finally, a plugin based on the Osate2 tool and a case study are given. © 2017 Totem Publisher, Inc. All rights reserved.