Low Power Multistage Test Data Compression Scheme

被引：0
|
作者：
Chen T. [1 ,2 ]
Yi X. [1 ,2 ]
Wang W. [1 ,2 ]
Liu J. [1 ,2 ]
Liang H.-G. [1 ,3 ]
Ren F.-J. [2 ,4 ]
机构：
[1] School of Computer and Information, Hefei University of Technology, Hefei, 230009, Anhui
[2] Anhui Province Key Laboratory of Affective Computing and Advanced Intelligent Machine, Hefei University of Technology, Hefei, 230009, Anhui
[3] School of Electronic Science & Applied Physics, Hefei University of Technology, Hefei, 230009, Anhui
[4] The University of Tokushima, Tokushima
来源：
Tien Tzu Hsueh Pao/Acta Electronica Sinica | 2017年 / 45卷 / 06期
关键词：
Low power test; Multistage compression; Test data compression; Test vector compatible;
D O I：
10.3969/j.issn.0372-2112.2017.06.015
中图分类号：
学科分类号：
摘要：
With the development of the integrated circuit(IC) manufacturing technology, very large scale integrated(VLSI) circuits test is faced with the problems of over large test data volume and high test power consumption. This paper presents a low-power multistage test data compression scheme to address these two problems. Firstly, the proposed scheme preprocesses the original test set with the input reduction technology so as to reduce the volume of specified bits; secondly, the scheme compresses test patterns shifted in multi-scan chains according to their compatibilities and uses shorter code to demonstrate compatible test patterns, namely the first stage of compression; thirdly, the low power X-filling is conducted: X-filling for capture power reduction is first conducted for the unspecified bits to keep the capture power under the given threshold and then the remaining unspecified bits are filled for shift power reduction; finally, the proposed scheme further compresses test patterns using modified run-length coding. Experimental results for ISCAS89 benchmark circuits demonstrate that, compared with golomb, FDR, EFDR, 9C, BM code, etc., the proposed scheme achieves better compression rate while reducing both the capture power and the shift power. © 2017, Chinese Institute of Electronics. All right reserved.
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页码：1382 / 1388
页数：6
相关论文
共 19 条
  • [1] Yuan H., Mei J., Song H., Et al., Test data compression for system-on-a-chip using count compatible pattern run-length coding, Journal of Electronic Testing: Theory and Applications, 30, 2, pp. 237-242, (2014)
  • [2] Han Y., Hu Y., Li X., Et al., Embedded test decompressor to reduce the required channels and vector memory of tester for complex processor circuit, IEEE Transactions on Very Large Scale Integration Systems, 15, 5, pp. 531-540, (2007)
  • [3] Chandra A., Chakrabarty K., System-on-a-chip test-data compression and decompression architectures based on Golomb codes, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 20, 3, pp. 355-368, (2001)
  • [4] Chandra A., Chakrabarty K., Frequency-directed run-length (FDR) codes with application to system-on-a-chip test data compression, Proceedings of the 19th IEEE VLSI Test Symposium, pp. 42-47, (2001)
  • [5] El-Maleh A.H., Test data compression for system-on-a-chip using extended frequency-directed run-length code, IET Computer and Digital Techniques, 2, 3, pp. 155-163, (2008)
  • [6] Zhan W., El-Maleh A., A new collaborative scheme of test vector compression based on equal-run-length coding (erlc), Proceedings of the 13th International Conference on Computer Supported Cooperative Work in Design, pp. 21-25, (2009)
  • [7] Tseng W.D., Lee L.J., Test data compression using multi-dimensional pattern run-length codes, Journal of Electronic Testing: Theory and Applications, 26, 3, pp. 393-400, (2010)
  • [8] Liang H.-G., Jiang C.-Y., Efficient test data compression and decompression based on alternation and run length codes, Chinese Journal of Computers, 27, 4, pp. 548-554, (2004)
  • [9] Zhan W.-F., Liang H.-G., Shi F., Et al., A test data compression scheme based on mixed fixed and variable run-length coding in virtual block, Acta Electronica Sinica, 37, 8, pp. 1837-1841, (2009)
  • [10] Jas A., Ghosh-Dastidar J., Ng M.E., Et al., An efficient test vector compression scheme using selective Huffman coding, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 22, 6, pp. 797-806, (2003)
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