A Fault-Tolerant Design of Spaceborne Onboard Neural Network

被引:0
|
作者
Chen Z. [1 ,2 ]
Zhang M. [1 ]
Zhang J. [3 ]
机构
[1] National Engineering Center of ASIC, Southeast University, Nanjing
[2] Nanjing Institute of Electronic Technology, Nanjing
[3] College of Computer Science and Electronic Engineering, Hunan University, Changsha
关键词
Fault-tolerate design; Field Programmable Gate Array (FPGA); Neural network; Single Event Upset (SEU);
D O I
10.11999/JEIT230378
中图分类号
学科分类号
摘要
In order to meet the application requirements of high reliability on-orbit real-time ship target detection, a fault-tolerant reinforcement design for ship target detection based on neural network in Synthetic Aperture Radar (SAR) is proposed. The tiny network MobilenetV2 is used for detection model, which implements the pipeline process in the Field Programmable Gate Array (FPGA). The influence of Single Event Upset (SEU) model on the FPGA is analyzed, which combines the idea of parallelization acceleration and high reliability Triple Module Redundancy (TMR). In this way a partial triple redundancy architecture based on dynamic reconfiguration is designed. The fault-tolerant architecture employs multiple coarse-grained compute units to process multiple images at the same time and uses multi-unit voting to perform single-event flip self-inspection and recovery. The frame rate meets the real-time processing requirements after the real image playback test. By simulating single event upset test, this fault-tolerant design method can improve the detection accuracy of anti-single particle flip by more than 8% when the resource consumption is only increased by less than 20%, which is more suitable for on-orbit applications than the traditional fault-tolerant design method. © 2023 Science Press. All rights reserved.
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收藏
页码:3234 / 3243
页数:9
相关论文
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