A Mixed Approach for Clock Synchronization in Distributed Data Acquisition Systems

被引:0
|
作者
Manduchi, Gabriele [1 ]
Rigoni, Andrea [1 ]
Trevisan, Luca [1 ]
Patton, Tommaso [1 ]
机构
[1] Consorzio RFX, Corso Stati Uniti 4, I-35127 Padua, Italy
关键词
timing systems; FPGA; SoC; RedPitaya;
D O I
10.3390/s24186155
中图分类号
O65 [分析化学];
学科分类号
070302 ; 081704 ;
摘要
Proper timing synchronization is important when data from sensors are acquired by different devices. This paper proposes a simple but effective solution for System on Chip (SoC) architectures that integrates a general-purpose Field Programmable Gate Array (FPGA) with a CPU. The proposed approach relies on a network synchronization protocol implemented in software, such as Network Time Protocol (NTP) or Precision Time Protocol (PTP), and uses the FPGA to generate a clock reference that is maintained in step with the synchronized system clock. The clock generated by the FPGA is obtained from the FPGA oscillator via appropriate fractional clock division. Clock drift is avoided via a software program that periodically compares the FPGA and the system counters, respectively, and adjusts the fractional clock divider in order to slightly adjust the FPGA clock frequency using a Proportional Integral controller. A specific implementation is presented on the RedPitaya platform, generating a 1 MHz clock in step with the NTP synchronized system clock. The presented system has been used in a distributed data acquisition system for fast transient recording in the neutral beam test facility for the ITER nuclear fusion experiment.
引用
收藏
页数:10
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