An Improved Hierarchy Physical Design Flow for High Speed Circuits

被引：0
|
作者：
Chen Y. [1 ]
Liang L. [1 ]
机构：
[1] Institute of Microelectronics, Chinese Academy of Sciences, Beijing
来源：
Hunan Daxue Xuebao/Journal of Hunan University Natural Sciences | 2018年 / 45卷 / 10期
基金：
中国国家自然科学基金;
关键词：
Area; Delay; High speed; Layout; Placement;
D O I：
10.16339/j.cnki.hdxbzkb.2018.10.016
中图分类号：
学科分类号：
摘要：
This paper proposed an improved hierarchical flow for physical design in deep sub-micron technology. This flow can reduce routing congestion and improve timing delay. The key point of this flow is to use the external connectivity information of the target block to design the floorplan, which could achieve a good place and route result in one iteration using quantitative analysis, saving time and efforts from multiple failed iterations. The proposed flow was tested on a large mux block in DSP design in SMIC 65 nm low leakage process, and the result showed it improved 20% in area and 35% in timing delay compared with the traditional flow. © 2018, Editorial Department of Journal of Hunan University. All right reserved.
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收藏
页码：115 / 120
页数：5
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