Device simulation of grain boundaries with oxide-silicon interface roughness in laser-crystallized polycrystalline silicon thin-film transistors

被引:0
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作者
Kimura, Mutsumi [1 ]
Eguchi, Tsukasa [2 ]
Inoue, Satoshi [1 ]
Shimoda, Tatsuya [1 ]
机构
[1] Base Technology Research Center, Seiko Epson Corporation, 3-3-5 Owa, Suwa 392-8502, Japan
[2] LT Business Development Center, Seiko Epson Corporation, 3-3-5 Owa, Suwa 392-8502, Japan
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关键词
Carrier concentration - Electric conductance - Grain boundaries - Interfaces (materials) - Laser applications - Polycrystalline materials - Semiconducting silicon - Surface roughness;
D O I
10.1143/jjap.39.l775
中图分类号
学科分类号
摘要
The effect of grain boundaries with oxide-silicon interface roughness on the transistor characteristics of laser-crystallized polycrystalline silicon thin-film transistors (poly-Si TFTs) was analyzed by device simulation. When grain boundaries and interface roughness are considered simultaneously, degradation of the on-current caused by grain boundaries is reduced by the interface roughness because the electric field concentration increases the carrier density and improves the conductance. It is interesting to note that reducing the interface roughness at the grain boundary does not always reduce the degradation of the transistor characteristics for the convex roughness in the laser-crystallized poly-Si TFTs.
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