An optimized analog layout for a Low Power 3-bit flash type ADC modified with the CMOS inverter based comparator designs

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作者：
Department of Electronics and Telecommunication Engineering, Jadavpur University, Kolkata, W. Bengal, India [1 ]
不详 [2 ]
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Proc. IEEE Int. Conf. Circuit, Power Comput. Technol., ICCPCT | 2013年 / 736-740期
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D O I：
10.1109/ICCPCT.2013.6528939
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摘要：
Comparators (optical)
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