共 32 条
- [2] Heterogeneous Multi-Core Architecture for a 4G Communication in High-Speed Railway [J]. 2015 10TH INTERNATIONAL DESIGN & TEST SYMPOSIUM (IDT), 2015, : 26 - 31
- [3] HIGH-SPEED MODELING OF CABLES AND CONNECTOR SYSTEMS [J]. PROCEEDINGS OF THE TECHNICAL CONFERENCE : NINTH ANNUAL INTERNATIONAL ELECTRONICS PACKAGING CONFERENCE, VOLS 1 AND 2, 1989, : 667 - 677
- [5] High-Speed Realization of Trivium Based on Multi-Core Cryptographic Processor [J]. PROCEEDINGS OF 2015 IEEE 11TH INTERNATIONAL CONFERENCE ON ASIC (ASICON), 2015,
- [6] Low-Overhead, High-Speed Multi-core Barrier Synchronization [J]. HIGH PERFORMANCE EMBEDDED ARCHITECTURES AND COMPILERS, PROCEEDINGS, 2010, 5952 : 18 - 34
- [7] Research on the IDSS of high-speed railway based on multi-agent [J]. PROCEEDINGS OF 2007 INTERNATIONAL CONFERENCE ON MANAGEMENT SCIENCE & ENGINEERING (14TH) VOLS 1-3, 2007, : 79 - 84
- [8] Channel Modeling for Future High-Speed Railway Communication Systems: A Survey [J]. IEEE ACCESS, 2019, 7 : 52818 - 52826
- [9] High-Speed Realization of Parallel Algorithm for Hash Computation On Multi-Core Cryptographic Processor [J]. PROCEEDINGS OF 2016 IEEE INTERNATIONAL CONFERENCE ON INTEGRATED CIRCUITS AND MICROSYSTEMS (ICICM), 2016, : 223 - 227
- [10] Analysis and Modeling for Train-Ground Wireless Wideband Channel of LTE on High-Speed Railway [J]. 2013 IEEE 77TH VEHICULAR TECHNOLOGY CONFERENCE (VTC SPRING), 2013,