共 50 条
- [1] Reduction of Power Dissipation during Scan Testing by Test Vector Ordering MTV 2007: EIGHTH INTERNATIONAL WORKSHOP ON MICROPROCESSOR TEST AND VERIFICATION, PROCEEDINGS, 2008, : 15 - +
- [3] Optimization techniques of static power dissipation in chip with dynamical threshold Dianzi Keji Daxue Xuebao/Journal of the University of Electronic Science and Technology of China, 2009, 38 (03): : 443 - 446
- [7] Reduction of Power Dissipation Through Parallel Optimization of Test Vector and Scan Register Sequences PROCEEDINGS OF THE 13TH IEEE SYMPOSIUM ON DESIGN AND DIAGNOSTICS OF ELECTRONIC CIRCUITS AND SYSTEMS, 2010, : 364 - 369
- [8] Expedited Response Compaction for Scan Power Reduction 2011 IEEE 29TH VLSI TEST SYMPOSIUM (VTS), 2011, : 40 - 45
- [9] Static test compaction for multiple full-scan circuits 21ST INTERNATIONAL CONFERENCE ON COMPUTER DESIGN, PROCEEDINGS, 2003, : 393 - 396
- [10] On static test compaction and test pattern ordering for scan designs INTERNATIONAL TEST CONFERENCE 2001, PROCEEDINGS, 2001, : 1088 - 1097