Research Progress on FPGA-based Machine Learning Hardware Acceleration

With the increasing production of massive data information and the widespread use of data mining applications in the fields of voice, languages, image, video, etc., people have entered the era of big data. In such an era, how to access data information efficiently and steadily and how to speed up the implementation of data mining applications have become the key issues that need to be solved urgently in academia and industry. And the machine learning algorithms, as the core component of data mining applications, have attracted more and more researchers' attention to applicate in various fields. Therefore, using existing hardware and software means to accelerate machine learning algorithms has become a research hotspot. In this study stocks boom, the current acceleration platforms can be summarized into four categories respectively: the custom logic circuits (such as FPGA/ASIC), the general graphics processing unit (GPGPU), the cloud computing platform and the heterogeneous computing platform. These acceleration platforms often show different parallel granularity and are suitable for different application scenarios. However, this is also a choice that they are combined to form heterogeneous systems to give full play to the processing capabilities of different acceleration devices. But, due to the customizable and high energy-efficient, the FPGA-based hardware acceleration is becoming a hot choice as the machine learning acceleration. Therefore, this paper mainly focuses on the field of machine learning algorithm accelerator based on FPGA. First of all, the paper introduces the machine learning algorithms and background knowledge in chapter 1&2. And then, we give the current development in this field, which composed of three parts (the methods for acceleration, the hardware platforms for acceleration and evaluations for accelerators) in chapter 3. And we propose an overview of the possible points of the accelerator with four sections. There are accelerating the kernel in the algorithm, abstracting the common feature in the algorithm, parallelizing algorithm and optimizing the data communication. After that, in chapter 4, the design and implementation of the current mainstream accelerators are introduced with four kinds of examples of various hardware machine learning accelerators, which is in order of specific issues, specific algorithm, common feature, and hardware template. Meanwhile, the structure of the design of accelerators is also simply classified and summarized in this chapter. The current hardware accelerator design is divided into two types, Stream and Single Engine. The characteristic of the Stream model is optimized for each calculation process in various hardware blocks and paralleled in the pipeline to achieve high performance. And the characteristic of the Single Engine model is focused on the common feature between all calculation process. Therefore, the Single Engine model could get larger and more hardware blocks than the Stream model to get high computation performance and compatibility. Finally, this paper summarizes the field of hardware-accelerated machine learning algorithms and puts forward the research direction and development trend in six points. In summary, this paper summarizes the current status of the development of machine learning accelerators and pointed out the future direction of development in the analysis of the current accelerator method. © 2020, Science Press. All right reserved.