Modeling Method for Testing Railway Signal System Software

被引：0
|
作者：
Li Y. [1 ]
Zhang X. [1 ]
Guo J. [2 ]
Zhang Y. [2 ]
机构：
[1] School of Optoelectronic Science and Engineering, University of Electronic Science and Technology of China, Chengdu
[2] School of Information Science and Technology, Southwest Jiaotong University, Chengdu
来源：
Xinan Jiaotong Daxue Xuebao/Journal of Southwest Jiaotong University | 2022年 / 57卷 / 02期
关键词：
Clock constraint; Modeling method; Railway signal system software; Risk level; Risk timed statechart; Z notation;
D O I：
10.3969/j.issn.0258-2724.20200530
中图分类号：
学科分类号：
摘要：
As the testing model of railway signal system software fails to describe the test requirements systematically, a risk timed statechart (RTSC) modeling method is proposed. First, the characteristics of testing railway signal system software are analyzed, and its modeling requirements are proposed. Then, based on the finite state machine (FSM) theory, the clock and risk level elements are extended respectively in the transition and state of the FSM, and the RTSC modeling method is proposed to meet the modeling requirements of the functional logic, clock constraint and risk level. The formal definition and configuration mechanism of the RTSC are expressed by Z notation. Finally, the switching function of computer-based interlocking system is used as an example to build the RTSC testing model and the proposed method is compared with the timed automata modeling method. The results show that in contrast to the timed automata modeling method, the RTSC saves 62% of transition numbers and has stronger description ability, which can meet the modeling requirements of the railway signal system software testing. Copyright ©2022 JOURNAL OF SOUTHWEST JIAOTONG UNIVERSITY. All rights reserved.
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页码：392 / 400and424
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