Column Level ADC Design Method of CMOS Image Sensor Based on Coarse and Fine Quantization Parallel and TDC Hybrid

Aiming at the speed bottleneck of traditional single-slope analog-to-digital converters (ADC) and serial two-step ADC in the readout process for large area array CMOS (Complementary Metal Oxide Semiconductor) image sensors, this paper proposes a fully parallel ADC design method for high-speed CMOS image sensors. Based on the idea of time sharing and time compression, the ADC design method advances the fine quantization time to the coarse quantization time period, which solves the time redundancy problem of the traditional method; at the same time, the interpolated time difference TDC (Time-to-Digital Converter) is used to realize the global Fast transition mechanism at low frequency clocks. Based on the 55-nm 1P4M CMOS process, this paper completes the detailed circuit design and comprehensive testing and verification of the proposed method. Under the analog voltage of 3.3 V, the digital voltage of 1.2 V, the clock frequency of 250 MHz, and the input voltage range of 1.2~2.7 V, the line time is compressed to 825 ns, the differential nonlinearity and integral nonlinearity of the ADC are +0.6/− 0.6 LSB and +1.6/− 1.2 LSB, respectively, the signal-to-noise-distortion ratio (SNDR) is 68.271 dB, the effective number of bits (ENOB) reaches 11.049 bit, column The inconsistency is less than 0.05%. Compared with the existing advanced ADC, the method proposed in this paper can ensure the low power consumption and high precision, while the ADC conversion rate is increased by more than 87.1%. Quantification provides some theoretical support. © 2024 Chinese Institute of Electronics. All rights reserved.