SDIM-ITM interface algorithm and time delay compensation for a power hardware-in-the-loop simulation of MMC-HVDC

被引：0
|
作者：
Li G. [1 ]
Wang Y. [1 ]
Xiong Y. [2 ]
机构：
[1] School of Electrical Engineering, Northeast Electric Power University, Jilin
[2] Beijing Jingxi Gas-fired Thermal Power Corporation, Beijing
来源：
Dianli Xitong Baohu yu Kongzhi/Power System Protection and Control | 2019年 / 47卷 / 03期
关键词：
MMC-HVDC; PHIL; SDIM-ITM interface; Simulation accuracy; Time delay compensation;
D O I：
10.7667/PSPC180162
中图分类号：
学科分类号：
摘要：
To deal with the accuracy problem of Power Hardware-In-the-Loop (PHIL) simulation for Modular Multilevel Converter-based HVDC (MMC-HVDC) caused by the power interface hardware, a phase-lead correction unit that simulates an first-order high-pass RC filter is designed for time delay compensation. In this paper, the MMC is modeled with Thevenin's equivalent circuit to derive the real time value of damping impedance for SDIM interface and reduce the calculation burden. The SDIM-ITM interface is adopted for MMC-HVDC PHIL simulation, where ITM interface acts as a driver and SDIM interface acts as an observer, and it shows high accuracy and stability under conditions of both change of operating point and fault. However, the physical simulation accuracy is influenced by the interface (or power amplifier) time delay. Thus the phase of AC voltage signal exciting power amplifier is compensated by the proposed phase-lead correction unit to further improve the physical simulation accuracy. The effectiveness of the proposed time delay compensation method is verified by simulation results. © 2019, Power System Protection and Control Press. All right reserved.
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页码：56 / 63
页数：7
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