High-Efficiency 2n-Parallel Fast FIR Algorithm and Its Implementation Method

被引：0
|
作者：
Hu J.-H. [1 ]
Zeng W.-Q. [1 ]
Fei C. [1 ]
Chen J.-N. [1 ]
机构：
[1] National Key Laboratory of Science and Technology on Communications, University of Electronic Science and Technology of China, Chengdu
来源：
| 1600年 / Univ. of Electronic Science and Technology of China卷 / 49期
关键词：
2[!sup]n[!/sup]-parallel; FFA; FIR filter; Hardware efficiency;
D O I：
10.12178/1001-0548.2018076
中图分类号：
学科分类号：
摘要：
Fast finite impulse response (FIR) algorithm (FFA) can break the limitation that the hardware complexity of traditional parallel algorithm linearly increases with the degree of parallelism, which can improve FIR algorithm efficiency. However, there is few research focusing on the general algorithm and implementation structure for high-parallelism FFA. In this case, we propose high-efficiency 2n-parallel general FFA and its implementation structure. We also provide the high-parallelism FFA structure with non-2n-parallelism. According to the algorithm analysis and hardware efficiency estimation, we know that the efficient 2n-parallel FFA algorithm and structure proposed in this paper can achieve significant advantage over traditional methods, and this advantage is becoming more obvious with the parallelism increasing. Thus, the proposed high-efficiency 2n-parallel FFA can be used for the implementation of high-parallelism FIR filters. © 2020, Editorial Board of Journal of the University of Electronic Science and Technology of China. All right reserved.
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页码：182 / 186
页数：4
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共 12 条
  • [1] Ariyadoost H., Kavian Y.S., Ansari-Asl K., Two dimensional systolic adaptive DLMS FIR filters for image processing on FPGA, 20th Iranian Conference on Electrical Engineering (ICEE2012), pp. 243-248, (2012)
  • [2] Zhang Y., He W., Hong W., Et al., Flat topped radiation pattern synthesis based on FIR filter concept, 2017 IEEE Asia Pacific Microwave Conference (APMC), pp. 751-754, (2017)
  • [3] Tian J., Li G., Li Q., Hardware-efficient parallel structures for linear-phase FIR digital filter, 2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS), pp. 995-998, (2013)
  • [4] Selvakumar J., Bhaskar V., Narendran S., FPGA based efficient fast FIR algorithm for higher order digital fir filter, 2012 International Symposium on Electronic System Design (ISED), pp. 43-47, (2012)
  • [5] Leigh G.M., Fast FIR algorithms for the continuous wavelet transform from constrained least squares, IEEE Transactions on Signal Processing, 61, 1, pp. 28-37, (2013)
  • [6] Kyritsis E., Pekmestzi K., Hardware efficient fast FIR filter based on Karatsuba algorithm, 2016 5th International Conference on Modern Circuits and Systems Technologies (MOCAST), pp. 1-4, (2016)
  • [7] Parker D.A., Parhi K.K., Area-efficient parallel FIR digital filter implementations, Proceedings of International Conference on Application Specific Systems, Architectures and Processors, pp. 93-111, (1996)
  • [8] Parhi K.K., VLSI Digital Signal Processing Systems: Design and Implementation, (2007)
  • [9] Tsao Y.C., Choi K., Hardware-efficient VLSI implementation for 3-parallel linear-phase FIR digital filterof odd length, 2012 IEEE International Symposium on Circuits and Systems, pp. 998-1001, (2012)
  • [10] Annangi S., Puli R., ASIC implementation of efficient 16-parallel fast FIR algorithm filter structure, 20178th International Conference on Computing, Communication and Networking Technologies (ICCCNT), pp. 1-5, (2017)
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