Research on Fast Parasitic Inductance Extraction Method for Power Module Based on Partial Element Equivalent Circuit With Multiport Network

被引：0

作者：

Zhou Y. ^{[1
]}

Chen Y. ^{[1
]}

Gao H. ^{[1
]}

Li C. ^{[1
]}

Luo H. ^{[1
]}

Li W. ^{[1
]}

He X. ^{[1
]}

机构：

[1] College of Electrical Engineering, Zhejiang University, Hangzhou

来源：

Zhongguo Dianji Gongcheng Xuebao/Proceedings of the Chinese Society of Electrical Engineering | 2022年 / 42卷 / 01期

基金：

浙江省自然科学基金; 国家杰出青年科学基金; 中国国家自然科学基金;

关键词：

Multi-block discretization; Multiport network model; Parasitic inductance; Partial element equivalent circuit; Power module;

D O I：

10.13334/j.0258-8013.pcsee.210462

中图分类号：

学科分类号：

摘要：

Numerical optimizations provide a new flexible and effective approach for the design of low-inductance and current-balance power modules, but meanwhile they set stricter requirements for efficiency of module inductance evaluations. To meet the demand of large-scale searches, based on the partial element equivalent circuit (PEEC) theory, a fast inductance extraction method with a multi-port network model was proposed. The method used the multi-port network model that was irrelevant to chip status to transform the problem of extracting overall and distribute inductances of the power module from multiple times solving of PEEC to a single-time decomposition of the circuit and solving of the port network. Besides, considering the plane and injection structure of layouts, a multi-block discretization strategy was proposed for wires and traces in straight and injection areas to reduce the filament quantity. The numerical and experimental results show that the calculation error of the method is less than 5%, which satisfies the need of engineering application, and the calculation time is reduced over 85% compared with the ANSYS Q3D software, made it suitable for fast optimization of power modules. © 2022 Chin. Soc. for Elec. Eng.

引用

页码：260 / 270

页数：10

共 33 条

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