Evaluation on Current Sharing of Power Module Affected by Kelvin Connection

被引:0
|
作者
Zeng Z. [1 ]
Li X. [1 ]
Cao L. [2 ]
Zhang X. [3 ]
机构
[1] State Key Laboratory of Power Transmission Equipment & System Security and New Technology, Chongqing University, Shapingba District, Chongqing
[2] CRRC Yongji Electric Co. Ltd., Yongji, 044502, Shanxi Province
[3] School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore
基金
国家重点研发计划;
关键词
Kelvin connection; Multi-chip power module; Parasitics model; Transient current sharing;
D O I
10.13334/j.0258-8013.pcsee.181343
中图分类号
学科分类号
摘要
High capacity power module with multiple chips in parallel is a key element for renewable energy integration and electrified transportation applications. Imbalance electro-thermal stress in a multi-chip power module challenges the high power capacity applications. Advanced packaging is considered as a promising solution toward next-generation power electronics. In this paper, based on a commercial power module packaging, to enhance the current sharing in the multi-chip power module, the capability of auxiliary Kelvin connection to limit the transient imbalance current among parallel chips was comparatively surveyed. Taking parasitics into account, electric circuit and finite element analysis were proposed to illustrate the influences of Kelvin connection. Based on customized power modules and a test rig, simulation and experimental results were presented to comprehensively demonstrate the current sharing of parallel chips affected by Kelvin connection. It reveals the capability to eliminate imbalance current by using Kelvin connection is limited. Optimized direct bonded copper (DBC) layout to eliminate the asymmetric loops is needed for multi-chip modules. © 2019 Chin. Soc. for Elec. Eng.
引用
收藏
页码:5480 / 5489
页数:9
相关论文
共 26 条
  • [1] Huang A.Q., Power semiconductor devices for smart grid and renewable energy systems, Proceedings of the IEEE, 105, 11, pp. 2019-2047, (2017)
  • [2] Wang F., Zhang Z., Ericsen T., Et al., Advances in power conversion and drives for shipboard systems, Proceedings of the IEEE, 103, 12, pp. 2285-2311, (2015)
  • [3] Li X., Zeng Z., Chen H., Et al., Comparative package evaluation and failure mode analysis of SiC, Si, and hybrid power modules, Proceedings of the CSEE, 38, 16, pp. 4823-4835, (2018)
  • [4] Peftitsis D., Baburske R., Rabkowski J., Et al., Challenges regarding parallel connection of SiC JFETs, IEEE Transactions on Power Electronics, 28, 3, pp. 1449-1463, (2013)
  • [5] Zeng Z., Shao W., Chen H., Et al., Changes and challenges of photovoltaic inverter with silicon carbide device, Renewable and Sustainable Energy Reviews, 78, pp. 624-639, (2017)
  • [6] Li X., Ran L., Zeng Z., Et al., Modeling and evaluating of temperature-frequency feature of paralleled PiN diodes, Proceedings of the CSEE, 38, 18, pp. 5405-5414, (2018)
  • [7] Li H., Munk-Nielsen S., Wang X., Et al., Influences of device and circuit mismatches on paralleling silicon carbide MOSFETs, IEEE Transactions on Power Electronics, 31, 1, pp. 621-634, (2016)
  • [8] Lim J.K., Peftitsis D., Rabkowski J., Et al., Analysis and experimental verification of the influence of fabrication process tolerances and circuit parasitics on transient current sharing of parallel-connected SiC JFETs, IEEE Transactions on Power Electronics, 29, 5, pp. 2180-2191, (2014)
  • [9] Hu J., Alatise O., Gonzalez J.A.O., Et al., Robustness and balancing of parallel-connected power devices: SiC versus CoolMOS, IEEE Transactions on Industrial Electronics, 63, 4, pp. 2092-2102, (2016)
  • [10] Hu J., Alatise O., Gonzalez J.A.O., Et al., The effect of electrothermal nonuniformities on parallel connected SiC power devices under unclamped and clamped inductive switching, IEEE Transactions on Power Electronics, 31, 6, pp. 4526-4535, (2016)