共 15 条
- [1] Murray K E, Whitty S, Liu S Y, Et al., Timing-driven titan: enabling large benchmarks and exploring the gap between academic and commercial CAD, ACM Transactions on Reconfigurable Technology and Systems, 8, 2, (2015)
- [2] Betz V, Rose J, Marquardt A., Architecture and CAD for deep-submicron FPGAs, (1999)
- [3] McMurchie L, Ebeling C., PathFinder: a negotiation-based performance-driven router for FPGAs, Proceedings of the 3rd International ACM Symposium on Field-Programmable Gate Arrays, pp. 111-117, (1995)
- [4] Murray K E, Petelin O, Zhong S, Et al., VTR 8: high-performance CAD and customizable FPGA architecture modelling, ACM Transactions on Reconfigurable Technology and Systems, 13, 2, (2020)
- [5] Liu Yang, Yang Haigang, Huang Zhihong, Et al., A fast FPGA routing algorithm based on repeated search avoidance, Journal of Computer-Aided Design & Computer Graphics, 26, 6, pp. 1015-1024, (2014)
- [6] Liu Yang, Yang Haigang, Yu Wei, Et al., An FPGA timing routing algorithm based on PathFinder and rip-up and retry approach, Journal of Computer-Aided Design & Computer Graphics, 26, 1, pp. 138-145, (2014)
- [7] Vahid F, Stitt G, Lysecky R., Warp processing: dynamic translation of binaries to FPGA circuits, Computer, 41, 7, pp. 40-46, (2008)
- [8] Coole J, Stitt G., BPR: fast FPGA placement and routing using macroblocks, Proceedings of the 8th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, pp. 275-284, (2012)
- [9] Shen M H, Luo G J, Xiao N., Combining static and dynamic load balance in parallel routing for FPGAs, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 40, 9, pp. 1850-1863, (2021)
- [10] Wang D K, Duan Z H, Tian C, Et al., ParRA: a shared memory parallel FPGA router using hybrid partitioning approach, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 39, 4, pp. 830-842, (2020)