Design of pipeline analog digital converter based on fully differential ring amplifier

被引：0
|
作者：
Chen M. [1 ,2 ]
Xiao J. [1 ,2 ]
Chen M. [1 ,2 ]
Chen J. [1 ]
机构：
[1] Institute of Microelectronics, Chinese Academy of Sciences, Beijing
[2] School of Microelectronics, University of Chinese Academy of Sciences, Beijing
来源：
Harbin Gongcheng Daxue Xuebao/Journal of Harbin Engineering University | 2019年 / 40卷 / 01期
关键词：
Analog-to-digital converter; ENOB; Fully differential; Pipeline; Ring amplifier; SNDR;
D O I：
10.11990/jheu.201709133
中图分类号：
学科分类号：
摘要：
This study aims to develop a low-power pipeline analog-to-digital converter (ADC). A new fully differential ring amplifier is developed and used to design a 10 bit 40MS/s pipeline ADC. The system is implemented with mixed signals by HHGRACE 0.18um 1P6M process technology. Simulation results indicate that for a 2.001 95 MHz sinusoid input, the system can achieve an effective number of bit of 9.74 bit, a maximum differential non-linearity of ±0.5 LSB, a maximum integral non-linearity of ±0.65LSB, and total ADC core power consumption of 5.32 mW. © 2019, Editorial Department of Journal of HEU. All right reserved.
引用
收藏
页码：196 / 201
页数：5
相关论文
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