3D Parallel ReRAM Computation-in-Memory for Hyperdimensional Computing

被引：0

作者：

Kihara, Fuyuki ^{[1
]}

Matsui, Chihiro ^{[1
]}

Takeuchi, Ken ^{[1
]}

机构：

[1] Univ Tokyo, Grad Sch Engn, Dept Elect Engn & Informat Syst, Tokyo 1138656, Japan

来源：

IEICE TRANSACTIONS ON ELECTRONICS | 2024年 / E107C卷 / 10期

关键词：

Computation-in-Memory; ReRAM; chain-cell memory; hyper-dimensional computing;

D O I：

10.1587/transele.2023CTS0001

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this work, we propose a 1T1R ReRAM CiM architecture for Hyperdimensional Computing (HDC). The number of Source Lines and Bit Lines is reduced by introducing memory cells that are connected in series, which is especially advantageous when using a 3D implementation. The results of CiM operations contain errors, but HDC is robust against them, so that even if the XNOR operation has an error of 25%, the inference accuracy remains above 90%.

引用

页码：436 / 439

页数：4

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