Efficient machine learning-assisted failure analysis method for circuit-level defect prediction

Integral to the success of transistor advancements is the accurate use of failure analysis (FA) which benefits in fine-tuning and optimization of the fabrication processes. However, the chip makers face several FA challenges as device sizes, structure, and material complexities scale dramatically. To sustain manufacturability, one can accelerate defect identification at all steps of the chip processing and design. On the other hand, as technologies scale below the nanometer nodes, devices are more sensitive to unavoidable process-induced variability. Therefore, metallic defects and process-induced variability need to be treated concurrently in the context of chip scaling, while failure diagnostic methods to decouple the effects should be developed. Indeed, the locating a defective component from thousands of circuits in a microchip in the presence of variability is a tedious task. This work shows how the SPICE circuit simulations coupled with machine learning based-physical modeling should be effectively used to tackle such a problem for a 6T-SRAM bit cell. An automatic bridge defect recognition system for such a circuit is devised by training a predictive model on simulation data. For feature descriptors of the model, the symmetry of the circuit and a fundamental material property are leveraged: metals (semiconductors) have a positive (negative) temperature coefficient of resistance up to a certain voltage range. Then, this work successfully demonstrates that how a defective circuit is identified along with its defective component's position with approximately 99.5 % accuracy. This proposed solution should greatly help to accelerate the production process of the integrated circuits.