Sub-10-GHz Cryo-CMOS LNAs Achieving Up to 0.07-dB Average NF Thanks to Back Biasing for Qubit Readout in 28-nm FD-SOI

被引：0

作者：

Puyal, V ^{[1
]}

Berlingard, Q. ^{[1
,2
]}

Lugo-Alvarez, J. ^{[1
]}

Blampey, B. ^{[1
]}

Casse, M. ^{[1
]}

Belot, D. ^{[3
]}

机构：

[1] Univ Grenoble Alpes, CEA Leti, Grenoble, France

[2] Univ Grenoble Alpes, Univ Savoie Mt Blanc, IMEP LAHC, CNRS,Grenoble INP, Grenoble, France

[3] STMicroelectronics, Grenoble, France

来源：

2024 IEEE/MTT-S INTERNATIONAL MICROWAVE SYMPOSIUM, IMS 2024 | 2024年

基金：

欧盟地平线“2020”;

关键词：

cryogenic CMOS; low noise amplifier; LNA; resistive-feedback inverter; quantum computing; qubit readout;

D O I：

10.1109/IMS40175.2024.10600229

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents cryogenic CMOS inverter-based low noise amplifiers (LNAs) for highly integrated quantum readout electronics. The circuits are fabricated in a 28-nm FD-SOI process. The LNAs consist of three stages: a first inverter stage for noise optimization, a second inverter stage for gain enhancement and a last output buffer stage for impedance matching. Four versions have been designed to cover all qubit readout sub-10-GHz scenarios. The LNAs are measured on a cryogenic on-wafer probe station at room temperature (RT: 300K) and at cryogenic temperature (CT: 4K). Thanks to the use of the back gate, the proposed circuits achieve, depending on the version, a noise figure (NF) of 1.2-2.6 dB and 0.13-0.54 dB at 300K and 4K, respectively. By pushing further the back gate voltage, a minimum NF of 0.07 dB at 4K is attained, corresponding to an ultra-low noise temperature of 4.7K.

引用

页码：870 / 873

页数：4