Decoupled Vector Runahead for Prefetching Nested Memory-Access Chains

被引：0

作者：

Naithani, Ajeya ^{[1
]}

Roelandts, Jaime ^{[1
]}

Ainsworth, Sam ^{[2
]}

Jones, Timothy M. ^{[3
]}

Eeckhout, Lieven ^{[1
]}

机构：

[1] Univ Ghent, B-9000 Ghent, Belgium

[2] Univ Edinburgh, Edinburgh EH8 9AB, Scotland

[3] Univ Cambridge, Comp Architecture & Compilat, Cambridge CB3 OFD, England

来源：

IEEE MICRO | 2024年 / 44卷 / 04期

基金：

英国工程与自然科学研究理事会; 欧洲研究理事会;

关键词：

Prefetching; Vectors; Out of order; Parallel processing; Microarchitecture; Hardware; Tracking loops;

D O I：

10.1109/MM.2024.3406891

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Decoupled vector runahead (DVR) exploits massive amounts of memory-level parallelism to improve the performance of applications that feature indirect memory accesses by dynamically inferring loop bounds at runtime, recognizing striding loads, and speculatively vectorizing the subsequent instructions that are part of an indirect chain. DVR runs as an on-demand, speculative, in-order, lightweight hardware subthread alongside the main thread within the core. DVR incurs minimal hardware overhead while delivering a substantial performance boost.

引用

页码：20 / 26

页数：7

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