FPGA Implementation of Physically Unclonable Functions Based on Multi-threshold Delay Time Measurement Method to Mitigate Modeling Attacks

Physically Unclonable Functions (PUFs) are security primitives that generate chip-specific responses by exploiting the subtle manufacturing variations in semiconductor devices. Arbiter PUF is a typical extensive PUF that has a large space for challenge-response pairs (CPRs); however, it is vulnerable to deep learning (DL) attacks predicting unknown CRPs. One of the approaches to mitigate DL attacks is the RG-DTM PUF, which utilizes the delay time measurement (DTM) method with a multi-offset sense amplifier; however, this technique is difficult to implement on FPGAs. In this paper, we propose a DTM method for FPGAs (fDTM) by placing multiple DFFs at unbalanced positions from the output of the delay paths. We implement the fDTM PUF on Xilinx Artix-7 and in a simulation and demonstrate its attack resistance against DL attacks. The experimental results show that the fDTM PUF achieves much higher attack resistance than the conventional Arbiter PUF with the equivalent area and achieves equivalent attack resistance to previous PUFs with areas around several to dozens of times smaller.