Unified-pipelined NTT Architecture for Polynomial Multiplication in Lattice-based Cryptosystems

Number Theoretic Transformation (NTT) is commonly employed to speed up polynomial multiplication in post quantum Lattice-Based Cryptography (LBC). A current trend in NTT hardware design involves using an iterative approach for forward and inverse NTT (INTT) computations. However, this iterative method demands substantial temporary memory and complex memory access patterns. This paper introduces a unified-pipelined NTT architecture for high-performance LBC cryptosystems. Our butterfly units employ a specially crafted Digital Signal Processing (DSP) for modular integer multiplication. Consequently, NTT and INTT calculations are carried out more swiftly with minimal hardware requirements, eliminating the need for DSP and Block Random Access Memory (BRAM). We applied this novel architecture to various parameter sets of LBC and implemented it on the Xilinx FPGA platform for comparison with state-of-the-art studies. Implementation results show that the proposed NTT architectures have outstanding hardware area and operating frequency improvements. The Area Time Product (ATP) is significantly improved, equivalent to at least 53% to 94% compared to the best designs reported to date.