Lightweight Extension of RISC-V Core for NTT-like Algorithms

Computing on the smallest Internet of Things (IoT) devices is increasingly essential. Dedicated hardware solutions, while offering high efficiency and speed, often lack the programmability required to adapt to evolving algorithms. Small CPUs, similar in energy consumption, usually cannot match this performance but can be enhanced through meticulous programming in assembly language. Typically, this improvement comes at the cost of increased code size or necessitates switching to a more energy-consuming platform. In this paper, we propose a combined hardware/software approach to enhance the performance of data-intensive algorithms on modified, efficient, small-sized RISC-V CPUs. We demonstrate this method using the Number Theoretic Transform from the Kyber algorithm as a case study. Our approach resulted in a significant speed improvement, while maintaining a code size that is nearly the same and reasonable resource utilization increase.