Stacked circuit packaging method of multichip SiC MOSFET power modules for electrical performance improvement

At present, most silicon carbide (SiC) power devices are packaged in traditional silicon (Si) packages, which suffer from the issue of excessive parasitic inductance. Therefore, this paper proposes a multi-chip SiC MOSFET power module stacking circuit packaging method to improve electrical performance. Instead of wire bonding technology, the planar interconnection technology is employed to achieve electrical connection between the chip surface electrode and the control terminal. By utilizing the principle of magnetic field cancellation, a stacked circuit with mutual inductance cancellation is constructed, and the thickness of the epoxy resin dielectric layer is controlled to enhance the effect of mutual inductance cancellation. Similarly, a stacked power terminal is built to further reduceparasitic inductance of the power module, thereby reducing the overall converter circuit's inductance to approximately 1.40 nH. A 1200 V, 36 A full SiC MOSFET power module is designed. The low parasitic inductance and high-speed switching characteristics of the power module are analyzed and validated through finite element simulation.