An Analog-assisted Fast-transient Digital LDO with a Charge-pump-based Fine Loop Achieving 0.14-mV Output Voltage Ripples

被引：0

作者：

Qaisar, Shirin ^{[1
]}

Akram, Muhammad Abrar ^{[2
]}

Farooq, Muhammad Haris ^{[1
]}

Kweon, Soon-Jae ^{[3
]}

Cheema, Hammad M. ^{[1
]}

Ha, Sohmyung ^{[2
,4
]}

机构：

[1] Natl Univ Sci & Technol NUST, Islamabad, Pakistan

[2] New York Univ Abu Dhabi, Abu Dhabi, U Arab Emirates

[3] Catholic Univ Korea, Bucheon, South Korea

[4] NYU, New York, NY USA

来源：

2024 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, ISCAS 2024 | 2024年

关键词：

Digital low-dropout regulator; analog-assistance; fast-transient; ripple-less; power efficiency; LOW-DROPOUT REGULATOR; POWER MANAGEMENT; HYBRID LDO;

D O I：

10.1109/ISCAS58744.2024.10557926

中图分类号：

TP39 [计算机的应用];

学科分类号：

081203 ; 0835 ;

摘要：

This paper presents a digital low dropout (DLDO) regulator, which has very small steady-state voltage ripples (VRIPP) of <140 mu V and a minimum dropout voltage of 20 mV, for driving both noise-sensitive analog and power-efficient digital load circuits in system-on-chip devices. To eliminate VRIPP, a steady-state control based on a voltage-to-interval converter and a charge pump is proposed. To achieve a fast transient response, a dual-edge-triggered shift registers (DTSR) is used in the coarse loop. In addition, an analog-assisted (AA) loop is proposed to significantly mitigate the voltage undershoot in response to a load current (ILOAD) step. The DLDO was designed and fabricated in a 180-nm CMOS process with an active area of 0.253 mm(2). The simulated results demonstrate that the proposed DLDO achieves a line regulation of 8 mV/V and a load regulation of 0.081 mV/mA while driving a maximum ILOAD of 75 mA with a peak current efficiency of 99.93 %.

引用

页数：5