A 0.01-to-2.6-GHz Two-Fold Current Reuse Dual Noise-Canceling LNA Achieving 6.8-K Noise Temperature for Quantum Applications

This brief presents a cryogenic inverter-based two-fold current reuse with a dual noise-canceling low-noise amplifier (LNA) in 40-nm CMOS. The proposed LNA consists of three stages: a current-reuse inverter-based input stage with shunt-resistive feedback and self-body bias (SBB) to mitigate the V-th increase and boost V-th under cryogenic temperature. The second stage is the dual auxiliary noise-canceling stage with an additional current reuse parallel transistor to enhance transconductance and suppress the noise of both the main amplifier and auxiliary amplifier. The last stage is a common-source post-amplifier for further gain enhancement. At 4 K, the LNA achieves a measured peak gain (S-21) of 31 dB, with a large 3-dB bandwidth from 10 MHz to 2.6 GHz and a minimum NF of 0.1 dB (corresponding to noise temperature T-N of 6.8 K) at 0.6 GHz under power dissipation of 8.6 mW. The circuit occupies a core area of 0.117 mm(2).