Package Design and Analysis of a 20-kV Double-Sided Silicon Carbide Diode Module With Polymer Nanocomposite Field-Grading Coating

To tackle the insulation challenges present in packaging medium-voltage (MV) silicon carbide (SiC) power devices, we developed a package design for a 20-kV SiC. This design incorporates a nonlinear resistive polymer-nanoparticle composite to boost insulation without compromising thermal performance. Employing a "sandwich" structure, where diodes are connected between direct-bonded copper (DBC) substrates, our approach minimizes parasitic inductance (< 4.5 nH) through a wire-bond-less design. According to thermal simulations, this configuration leads to a junction temperature reduction up to 53.5 degrees C. The submodule configuration not only cuts the total deformation by a factor of three but also enhances both reliability and manufacturability. By coating the electrode triple points with the resistive composite, electric field (E-field) stress is diminished. Experimental tests indicated a 96% rise in the partial discharge (PD) inception voltage of substrates, increasing from 15.6 to 30.6 kV. For validation, scaled-down packages equipped with SiC diodes exceeding 16 kV were fabricated and put through rigorous testing.