Open-Source Elastic CGRA Generator

Coarse-Grained Reconfigurable Architectures (CGRAs) are a good choice for computing heavy data workloads in domain-specific application scenarios, as they are flexible enough to compute multiple kernels with more energy efficiency than Field-Programmable Gate Arrays (FPGAs), while at the same time featuring less configuration overheads. However, when working with these architectures, the selection of certain structural parameters is not trivial: the size, shape, and positions of the inputs and outputs from where loads and stores have to be done need to be carefully thought out during the design stages. In addition, the impact of these parameters on execution performance needs to be analyzed together with the memory infrastructure and the control interface when using a CGRA as the core computing fabric in a hardware accelerator. In this work, we provide an architectural template of an elastic CGRA, an automated generator of both the Register-Trasfer Logic (RTL) code and the configuration bitstreams to set a given functionality in a Processing Element (PE), and a simulator for the generated hardware.