Exploration of Network Interface Architectures for a Real-Time Network-on-Chip

被引：0

作者：

Schoeberl, Martin ^{[1
]}

机构：

[1] Tech Univ Denmark, Dept Appl Math & Comp Sci, Lyngby, Denmark

来源：

2024 IEEE 27TH INTERNATIONAL SYMPOSIUM ON REAL-TIME DISTRIBUTED COMPUTING, ISORC 2024 | 2024年

关键词：

network-on-chip; network interface; real-time systems; time-predictable computer architecture;

D O I：

10.1109/ISORC61049.2024.10551364

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

Network interfaces play a central role in multicore architectures that use a network-on-chip for communication. Network interface designs have not received much attention in the research community despite this central role. This paper explores different network interface configurations for a real-time network-on-chip architecture. We evaluate the effects of different FIFO queue organizations on the bandwidth and maximum latency of messages in a time-division multiplexing network-on-chip.

引用

页数：8

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