A Fast Transient Response Capless LDO Regulator Achieving-78 dB of PSR Up to 2 MHz

This paper presents a fast transient response capless low-dropout (LDO) regulator in 65 nm CMOS process for system-on-chip (SOC). The LDO regulator utilizes a feedforward ripple cancellation circuit (FFRCC) to achieve high power supply rejection (PSR), and a voltage damper is used to enhance transient response. Besides, a negative capacitance circuit (NCC) is added to the gate of the power stage to expand the bandwidth of FFRCC. The proposed LDO regulator is fabricated in 65 nm CMOS technology. Its voltage recovery time is 1.1 mu s and 400 ns, respectively, when the load current steps from 200 mu A to 50 mA or 50 mA to 200 mu A with the rise/fall time of 100 ns. Its overshoot and undershoot voltages are 114 mV and 98 mV, respectively. Moreover, the regulator achieves -78 dB PSR at 2 MHz.