A 128 Gb/s LDPC Decoder Using Partial Syndrome-based Dynamic Decoding Scheme for Terahertz Wireless Multi-Media Networks

被引：0

作者：

Wu, Tsung Han ^{[1
]}

Yeh, Ching Liang ^{[1
]}

Huang, Yi-Shan ^{[1
]}

Jou, Shyh Jye ^{[1
]}

机构：

[1] Natl Yang Ming Chia Tung Univ, Inst Elect, Hsinchu, Taiwan

来源：

2024 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, ISCAS 2024 | 2024年

关键词：

low-density parity check (LDPC) decoder; message-passing schedule; 6G; Terahertz; dynamic decoding;

D O I：

10.1109/ISCAS58744.2024.10558369

中图分类号：

TP39 [计算机的应用];

学科分类号：

081203 ; 0835 ;

摘要：

This paper presents a low power and high throughput multi-framed pipelined LDPC decoder architecture based on a novel partial syndrome-based dynamic decoding (PSDD) approach. The proposed PSDD can reduce clock cycle to allow the LDPC decoder to be implemented with better energy efficiency. We propose a high throughput sorting method and implement the LDPC decoder with a pipelined multi-frame VLSI architecture. The implementation results for the IEEE 802.15.3d Thz standard shows that the proposed design has a coding gain of 10(-8) at the specified SNR of 18.1 dB with 16 QAM modulation. Furthermore, the proposed design can achieve a throughput rate of 128.5 Gbps with the 16nm FinFET CMOS process, respectively.

引用

页数：5